1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and, particularly to a semiconductor device in which a plurality of contact plugs are closely formed and a manufacturing method thereof.
2. Description of Related Art
A number of transistors in a semiconductor device are formed on a silicon substrate. Source regions and drain regions of the transistors are connected to wiring patterns or various elements formed on upper layers via various contact electrodes. For example, either the source region or the drain region of a cell transistor are connected to bit line via a cell contact plug and a bit contact plug in a DRAM (Dynamic Random Access Memory), which is a typical semiconductor device (see Japanese Patent Application Laid-open No. 2008-72132).
FIGS. 26 to 31 are process diagrams for explaining a general method of connecting either the source regions or the drain regions in a DRAM to bit lines. FIGS. 26A, 28A, and 30A are schematic plan views in each process, FIGS. 26B, 28B, and 30B are schematic cross-sectional views taken along a line X-X in each of the plan views, FIGS. 27A, 29A, and 31A are schematic cross-sectional views taken along a line Y-Y in each of the plan views, and FIGS. 27B, 29B, and 31B are schematic cross-sectional views taken along a line Z-Z in each of the plan views.
As shown in FIGS. 26A, 26B, 27A and 27B, a plurality of transistors are formed by forming a plurality of gate electrodes 31, and a plurality of source regions and drain regions 32 on a semiconductor substrate 300. After forming a cap insulation film 33 composed of a silicon nitride film covering the side and top surfaces of each gate electrode 31, a first inter-layer insulation film 34 covering the plurality of transistors is formed. Cell contact plugs 35 connected to either the source regions or the drain regions 32 are formed in the inter-layer insulation film 34, and a second inter-layer insulation film 36 is formed thereon. Subsequently, a plurality of contact holes 37 exposing the top surfaces of the cell contact plugs 35 are formed in the inter-layer insulation film 36. As shown in FIGS. 28A, 28B, 29A and 29B, an conductive material filling the plurality of contact holes 37 is formed, which is flattened by CMP (Chemical Mechanical Polishing) to form a plurality of bit contact plugs 38. By patterning the conductive material, subsequent to formation thereof on the bit contact plugs 38, a plurality of bit lines 39 are formed, each of which connecting to each bit contact plug 38, as shown in FIGS. 30A, 30B, 31A and 31B.
With a manufacturing method shown in FIGS. 26A to 31B, there has been a possibility of short-circuiting between adjacent contact plugs 38 as the array pitch of the bit contact plugs 38 (contact holes 37) become very narrow due to progress of high integration. Therefore, there has been a problem that a very high precision is required for lithography and patterning (etching) to form the contact holes 37.
While conventional problems related to the present invention have been explained above by exemplifying a memory cell of a DRAM, these problems can similarly occur to other semiconductor devices.